3D NAND Flash

memory & tft

3D NAND flash

NAND flash memory technologies have changed from two-dimensional (2D) to three-dimensional (3D) structures to solve scaling issues in 2D structures such as cell-to-cell interference problems.

NAND flash memory technologies have changed from two-dimensional (2D) to three-dimensional (3D) structures to solve scaling issues in 2D structures such as cell-to-cell interference problems. Several 3D NAND flash memories such as BiCS, P-BiCS, TCAT, VG-NAND, and SMArT have been previously presented. Contrary to a 2D structure, channels are formed in a 3D structure after filling inner layers of vertical cylindrical memory holes. Because these channels should be vertically formed in the 3D structure, channel materials have been changed from single-crystal silicon to poly-silicon (poly-Si). However, poly-Si channels exhibit critical issues such as low effective channel mobility, threshold voltage instability, and poor reliability. These problems are known to be primarily due to the defects, generated at the grain boundary of the poly-Si channel, which interrupt the current conduction.

 In our study, we strive to improve the material properties of poly-Si channels for 3D NAND flash memory devices.

NAND 플래시 메모리 기술은 2차원 (2D) 구조에서의 스케일링 문제 (ex. Cell 간 간섭)를 해결하기 위해 3차원 (3D) 구조로 발전해 왔으며, BiCS, P-BiCS, TCAT, VG-NAND, SMArT등의 다양한 형태로 발표되고 있다. 이러한 구조에서는 2D 구조와는 달리 채널을 원통 수직형으로 형성시켜야 하므로 채널 물질로는 단결정 실리콘 (single-crystal silicon) 대신 다결정 실리콘 (poly-Si)이 사용되어진다. 이때, poly-Si 물질을 사용한 채널은 grain boundary에서 생성된 결함으로 인해 전류 전도가 방해되어 낮은 이동도, 불안정한 임계 전압 및 낮은 신뢰성을 갖게 되는 등 다양한 문제가 발생된다.

 본 연구실에서는 3D NAND 플래시 메모리의 성능 및 신뢰성 향상을 높이기 위해 poly-Si 채널의 재료 특성 및 구조에 대한 연구에 집중하고 있다.

 

 

 

 

 

대표업적

Applied Surface Science 477, 104-110 (2019)
IF 3.387; JCR 2.632%
“Variation of poly-Si grain structures under thermal annealing and its effect on the performance of
TiN/Al2O3/Si3N4/SiO2/poly-Si capacitors”

3D NAND Flash

3D NAND Flash
Samsung Electronics
Toshiba
Technical issues
  • Vertical charge loss through top and bottom oxides
  • Lateral migration toward spacers
  • Threshold voltage shift
  • Vertical hole design limitations
  • Generation of gain boundary in poly-Si
  • Reliability issue due to Interface trap
Fabrication & Data Gathering
Analysis
Reliability test
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